ARM Accredited Engineer v6.0 (EN0-001)

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Total 210 questions

Literal pool loads to access constants at run-time can be minimized by:

  • A. Ensuring constants can be encoded as immediates in the current instruction set.
  • B. Storing the code in ROM.
  • C. Using Thumb code rather than ARM code.
  • D. Compiling and linking as position-independent code.

Answer : A

The interval of time from an external interrupt request signal being raised to the first fetch of an instruction of the interrupt handler is called the interrupt:

  • A. Latency
  • B. Priority
  • C. Service thread
  • D. Jitter

Answer : A

In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)

  • A. Processor reset
  • B. Switching from ARM to Thumb state
  • C. Changing the access permissions of a page
  • D. Executing a Data Memory Barrier instruction
  • E. Loading data from an unaligned memory address

Answer : A,C

An ARM Cortex-A9 multi-core system has two CPUs, C1 and C2, each with a corresponding data cache. The code running on C1 writes to a memory location M. and C1 updates its data cache, but not main memory. After that, C2 tries to read the contents of memory location M. Which of the following hardware can automatically (without software inteivention) ensure that C2 reads the updated contents of M?

  • A. Snoop Control Unit
  • B. Tightly Coupled Memory
  • C. Level 2 Cache Controller
  • D. Dynamic Memory Access Controller

Answer : A

In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:
-> CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code.
-> CPU 3 is sleeping in low-power state following a WFE instruction.
CPU 2 executes a SEV instruction. What is the effect on the system?

  • A. CPU 0: executing, CPU 1: executing, CPU 2: executing. CPU 3: executing
  • B. CPU 0: executing, CPU 1: executing. CPU 2: executing. CPU 3: sleeping
  • C. CPU 0: sleeping, CPU 1: sleeping. CPU 2: executing. CPU 3: executing
  • D. CPU 0: sleeping, CPU 1: sleeping. CPU 2: sleeping, CPU 3: executing

Answer : C

Which one of the following features must any processor support to conform to the ARMv7-
A architecture?

  • A. NEON (Advanced SIMD)
  • B. Thumb-2 technology
  • C. TrustZone (Security Extensions)
  • D. Generic Interrupt Controller

Answer : B

The Q-flag in the program status register (PSR) indicates which of the following?

  • A. Arithmetic overflow has occurred
  • B. Processor is in Thumb execution state
  • C. Imprecise data aborts are currently disabled
  • D. Saturation has occurred after execution of a saturated arithmetic instruction

Answer : D

Why does Device memory prohibit speculative accesses?

  • A. Speculative accesses might waste energy
  • B. Speculative accesses might reduce performance
  • C. Speculative accesses might cause unwanted cache coherency traffic
  • D. Speculative accesses might cause undesired system state changes

Answer : D

What will be the contents of R2 after the execution of the following piece of code?


MOV R2, #0x4 -

ANDSR1, R1, #0x4 -

ADDNE R2, R2, #0x4 -

  • A. R2 = 0x4
  • B. R2 = 0x8
  • C. R2 = 0xAABBCCDD
  • D. R2 = 0xAABBCCD4

Answer : B

Which of these processors is only available as a single core configuration?

  • A. Cortex-A5
  • B. Cortex-A8
  • C. Cortex-A9
  • D. Cortex-A15

Answer : B

A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:

The second CPU receives the message using the instructions:

On both CPUs, r1 = 0x5000 and r2 = 0x6000. At which of the points A, B, C and D must
Data Memory Barrier (DMB) instructions be placed in order to ensure messages are passed reliably and efficiently?

  • A. A only
  • B. C only
  • C. B and C
  • D. A and D

Answer : D

To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?

  • A. PC=LR
  • B. PC=LR44
  • C. PC=LR-4
  • D. PC=LR-8

Answer : D

When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?

  • A. The linker
  • B. The archiver
  • C. The compiler
  • D. The assembler

Answer : A

Which of the following is preserved in dormant mode?

  • A. Core register contents
  • B. CP15 (system) register settings
  • C. Debug state
  • D. Cache contents

Answer : D

In an ARMv7-A processor that includes the Advanced SIMD extension (NEON), where are the data values operated on by NEON instructions stored?

  • A. In system memory
  • B. In registers shared with the VFP register set
  • C. In registers shared with the integer register set
  • D. In dedicated registers not shared with other registers

Answer : B

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Total 210 questions