Literal pool loads to access constants at run-time can be minimized by:
Answer : A
The interval of time from an external interrupt request signal being raised to the first fetch of an instruction of the interrupt handler is called the interrupt:
Answer : A
In a Cortex-A processor, after which TWO of these events is a cache maintenance operation required to ensure reliable code execution? (Choose two)
Answer : A,C
An ARM Cortex-A9 multi-core system has two CPUs, C1 and C2, each with a corresponding data cache. The code running on C1 writes to a memory location M. and C1 updates its data cache, but not main memory. After that, C2 tries to read the contents of memory location M. Which of the following hardware can automatically (without software inteivention) ensure that C2 reads the updated contents of M?
Answer : A
In a multi-processor system, there are four processors numbered 0, 1, 2 and 3. The state of the processors is as follows:
-> CPU 0 and 1 are sleeping in low-power state following a WFI instruction. . CPU 2 is executing program code.
-> CPU 3 is sleeping in low-power state following a WFE instruction.
CPU 2 executes a SEV instruction. What is the effect on the system?
Answer : C
Which one of the following features must any processor support to conform to the ARMv7-
A architecture?
Answer : B
The Q-flag in the program status register (PSR) indicates which of the following?
Answer : D
Why does Device memory prohibit speculative accesses?
Answer : D
What will be the contents of R2 after the execution of the following piece of code?
LDRR1, =0xAABBCCDD -
MOV R2, #0x4 -
ANDSR1, R1, #0x4 -
ADDNE R2, R2, #0x4 -
Answer : B
Which of these processors is only available as a single core configuration?
Answer : B
A message passing system between two CPUs is implemented using data stored in a shared area of memory. To pass a message, the first CPU executes the instructions:
Answer : D
To return from a Data Abort handler and re-execute the aborting instruction, what value should be loaded to the PC?
Answer : D
When building code for both ARM and Thumb states, which tool decides for each function call whether to use a BL or BLX instruction?
Answer : A
Which of the following is preserved in dormant mode?
Answer : D
In an ARMv7-A processor that includes the Advanced SIMD extension (NEON), where are the data values operated on by NEON instructions stored?
Answer : B